This new processor is aimed at emerging workloads such as deep learning, self-driving cars, autonomous drones, which ‘require an order of magnitude boost in processing efficiency to unlock their true potentials’ according to Andreas Olofsson, CEO, and Founder at Adapteva.

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The chip ‘Epiphany-V’ contains an array of 1024 64-bit RISC processors, 64MB of on-chip SRAM, three 136-bit wide mesh Networks-On-Chip, and 1024 programmable IO pins. The chip has taped out and is being manufactured by TSMC.

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Each node in the processor array is a complete RISC processor capable of running an operating system (“MIMD”). Epiphany uses a flat cache-less memory model, in which all distributed memory is readable and writable by all processors in the system.

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Now that the research has been completed Olofsson commented that the next stage of the project would be to 'fully characterise the Epiphany-V silicon devices once devices return from the foundry.'

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'Future work will focus on extending and customising the Epiphany-V SOC platform for specific target applications’ concluded Olofsson.

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This is the fifth generation of the Epiphany product line and includes new capabilities compared to previous iterations including; 64-bit memory addressing, 64-bit floating point operations, 2X the memory per processor, and custom ISAs for deep learning, communication, and cryptography.

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Olofsson explained that the primary goal of the project was ‘build a parallel processor with 1024 RISC cores demonstrating a processing energy efficiency of 75 GFLOPS/Watt. A secondary goal of this project is to demonstrate a 100x reduction in chip design costs for advanced node ASICs.’

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Adapteva released a paper detailing the technology which explains that the Epiphany architecture is a ‘distributed shared memory architecture comprised of an array of RISC processors communicating via a low-latency mesh Network-on-Chip.’

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Competition in the HPC processor market is building with the news that Adapteva, a specialist in the design of energy efficient accelerator chips and compute modules, has created a 1024 core processor – thanks, in part, due to a grant from the US, Defense Advanced Research Projects Agency (DARPA).

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