Ans: This tool should be used during memory IP generation in IP Catalog to enter accurate Board Skew Parameter Values calculated from the user's PCB delay. The tool calculates these Board Skew Parameters accurately and displays it to you on the "Skew Calculations" Page. These parameters are entered under the Board Timing Tab > Board and Package Skew in the IP Catalog GUI.

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This sheet holds the calculated skew which needs to be entered into the External Memory Interface IP parameter's board skew tab. It is highly recommended to use this calculated delay for IP generation to get accurate timing closure.

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For re-calculation, please restart the entire process by going back to the first sheet(Introduction Sheet) using the back button. Doing so will reset all global variable assignments to initial values and avoid any incorrect calculation which occurs due to the use of global variables with non-initial values.

Ans: The tool calculates board skew parameters according to Altera's recommended formula best suited for using our FPGA products.

Choose the protocol you want to calculate board skew parameters for (should match the protocol chosen in the Altera IP Catalog

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Ans: The tool can be found under Board Skew Parameter Tool (XLS) on Altera's External Memory Interface Solutions Center:

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ii. Please enter a value between the maximum and minimum table delays for all unused blank spaces. For Example. If there are 3 CK trace delay cells and you only want to use 2, choose one of the actual trace delay values from the two cells and copy it into the 3rd cell. The tool will use 0 as the minimum trace delay if left blank which will lead to wrong Board Skew Parameter calculations

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Selecting the option of clamshell or no clamshell during the IP configuration pop-up window in BSPT, will not have any impact. This selection was created specifically for No clamshell configuration.

iii. Enter delays inside the whitespaces only. If users modify any non-white areas, the tool may calculate inaccurate board skews

PCB traces can have skews between them which can cause timing margins to be reduced. Further, margin reduction can occur due to skews between different ranks in multi-rank topologies. With the increase in operating frequencies for memory interfaces, it has become increasingly important to enter accurate Board Skew Parameters for the External Memory Interfaces IP during the IP Catalog flow. This tool will enable you to calculate these board skew parameters faster and more easily. You can calculate these parameters by selecting your memory interface configuration and then entering in simulated trace delays for memory interface traces. For "How to Simulate", please refer to this FPGA wiki article:  Arria 10 EMIF Simulation Guidance

Choose either the Arria 10 IP button for Arria 10 External Memory Interfaces IP or UniPHY IP button for UniPHY External Memory Interfaces IP depending on the interface you have chosen in the Altera IP Catalog.

This tool is targeted to be used in Microsoft Excel 2010. You may face compatibility issues with earlier versions of Excel.

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iv. Enter in package delays for traces you plan to deskew with board traces (The tool will calculate the total delay for you)

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